Some of the keys to fabricating a high speed bipolar junction transistor are to not only fabricate a device which is intrinsically fast but also to reduce the parasitic resistances and capacitances associated with that device. Self-aligned structures and semiconductor-on-insulator structures combined with aggressively scaled base width and emitter/base/collector doping profiles represent prior art efforts toward obtaining high-speed bipolar devices and circuits. Recently, low-temperature, high-quality homo or heterojunction epitaxial techniques have significantly advanced the art of emitter-base-collector profile optimization for ever faster intrinsic homo or heterojunction bipolar devices. The prior art, however, has left something to be desired with respect to parasitic resistances and capacitances such as extrinsic base resistance, collector-base and collector-substrate capacitances, etc. which have not been dealt with adequately, especially in structures with very thin base layers formed by low temperature epitaxial deposition methods.
One prior art approach which deals with reducing the capacitance of base-emitter and base-collector junctions and the base resistance is shown in U.S. Pat. No. 4,499,657 initially filed on Feb. 29, 1980. In this patent, a lightly doped silicon layer is epitaxially grown on an oxide film with predetermined openings disposed on one main face of a silicon substrate to form single crystal portions in the openings and polycrystalline portions over the oxide. Ion implantation and thermal annealing are used to convert the polycrystalline portions to opposite conductivity type external base regions and form opposite conductivity internal base regions in the single-crystal portions. Arsenic ions are selectively implanted into the internal base region to form n-conductivity type emitter regions.
The approach of the patent depends on the different rates of dopant diffusion in single-crystal and polycrystalline semiconductor material to form intrinsic and extrinsic base regions. Under such circumstances where ion implantation and annealing are utilized in conjunction with a relatively thick semiconductor layer depth control of the base regions doesn't present a great problem. However, where the layer in which the base is to be formed is relatively thin, other approaches including in situ doping of the upper portion of an epitaxial layer must be used. Without the control provided by such an approach, it is very difficult to control the formation of a thin intrinsic base in which emitter regions must be ultimately formed. Also, in the patent, it is noted that the emitter and base regions are nonself-aligned resulting in the inevitable displacement to one side or the other of the emitter relative to the collector. As a result, link resistance is not readily controlled and is generally larger, by definition, than in a self-aligned structure. In the reference, the extrinsic base is aligned to the edge of the isolation. The intrinsic base should be aligned to the emitter diffusion edge otherwise high base resistance results which degrades switching performance. Thus, the reference patent cannot provide for self-alignment of the emitter and base nor is its fabrication approach susceptible to the fine control required when forming an emitter in intrinsic base regions.
In another prior art approach shown in U.S. Pat. No. 4,504,332 originally filed Sep. 6, 1979, the different rates of diffusion of a dopant in single-crystal and polycrystalline materials are utilized. Also the different oxidation rates of single-crystal and polycrystalline materials are utilized to provide a fully self-aligned bipolar structure. In the patent, a plurality of dielectric layers are used to surround an exposed region of semiconductor in which a subcollector is formed. The uppermost dielectric layer is doped with a p-type dopant. An epitaxial layer of n-type semiconductor material is deposited over the doped oxide where it deposits as polycrystalline material and over the exposed region of semiconductor where it deposits as single-crystal material. An annealing step out-diffuses p-type dopant into the polycrystalline material leaving the single-crystal material n-type. Then an oxidation step forms thin oxide over the single-crystal n-type material and a thick oxide over the polycrystalline regions. An etch step removes only the thin oxide and a p-type intrinsic base is implanted. After this, an n-doped oxide layer is deposited and out-diffused to form the emitter of the device.
The above cited reference relies on high temperature oxidation and annealing steps whereas the present approach utilizes low temperature oxidation in conjunction with in situ intrinsic base doping early in the process to provide good control of the extent of the extrinsic base as well as easy interconnection of the intrinsic and extrinsic bases. Also, the process of the reference is not consistent with the emitter depth requirement of present bipolar devices.
It is, therefore, an object of the present invention to provide a raised base, bipolar transistor in which the emitter, collector pedestal and intrinsic base are all self-aligned.
Another object is to provide a bipolar transistor which incorporates a composite dielectric layer in its final structure and permits the fabrication steps of the transistor to be carried out.
Another object is to provide a method of fabricating a raised base, bipolar transistor in which an oxidizable layer of polycrystalline disposed over oxide-nitride layers carries out many functions in its oxidized and unoxidized states.
Yet another object is to provide a method of fabricating a bipolar transistor in which a single lithographic and masking step permits self-alignment of the emitter, intrinsic and extrinsic bases and collector pedestal.
Yet another object is to provide a method of fabricating a bipolar transistor which provides a device having low base resistance and low capacitance.
These and other features and advantages of the present invention will become more apparent from the following more particular description of the preferred embodiment taken in conjunction with the following briefly described drawings.